1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for affecting dispatch and/or disposition of wafers.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using the patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used as, for example, a gate electrode structure for transistors. Many times, trench isolation structures are also formed across the substrate of the semiconductor wafer to isolate electrical areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The semiconductor wafer 105 typically includes a plurality of individual semiconductor die 103 arranged in a grid 150. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed across one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on approximately one to four die 103 locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to FIG. 2, a typical flow of processes performed on a semiconductor wafer 105 by a semiconductor manufacturing system is illustrated. A set of processing tools may be identified to be used to process wafers 105 (block 210). At each operation, wafers 105 may be processed by the tools based upon a number of manufacturing factors (block 220). Upon processing of at least a few semiconductor wafers 105, the manufacturing system may acquire metrology data relating to the processed semiconductor wafers 105 (block 230). Upon acquisition of the metrology data, the manufacturing system may then analyze the data to detect errors that may have occurred during the processing of the semiconductor wafers 105 (block 240). Based upon the analysis of the metrology data, the manufacturing system may adjust one or more manufacturing processes based upon the errors detected (block 250). Upon adjustments of the processes, the manufacturing system may continue processing of the semiconductor wafers 105 based upon the predetermined routing scheme (block 260).
Among the problems associated with the prior art methodology includes a lack of efficient reaction, particularly in terms of routing semiconductor wafers 105 throughout a manufacturing facility, based upon the processing errors. Some semiconductor wafers 105 in a batch/lot or some lots themselves may contain errors such that the functional yield relating to devices manufactured from the processed semiconductor wafers 105 may become unacceptably low. However, today's common methodologies generally call for the semiconductor wafers 105 being stepped through various manufacturing areas in a manufacturing facility based upon predetermined tool dedication and dispatch rules. Attempts to correct the errors may be made as they are routed based upon a predetermined routing scheme. However, feedback and/or feed forward corrections made to processes in the manufacturing facility may not be sufficient to improve the yield of the devices produced from the processed semiconductor wafers 105 in an efficient manner.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.